Readings.in.Computer.Architecture.rar
其中包括:
00 CAreadings_toc
01 Architecture of the IBM System 360
02 Parallel Operation in the Control Data 6600
03 The CRAY 1 computer system
04 cray 1 computer technology
05 cramming more components onto integrated circuits
06 the history of the microcomputer invention and evolution
07 Validity of the Single Processor Approach to Achieving Large Scale Computing Capabilities
08 Evaluating Associativity in CPU Caches
09 A Characterization of Processor Performance in the vax 11 780
10 Compilers and Computer Architecture
11 The 801 Minicomputer
12 The Case for the Reduced Instruction Set Computer
13 Computers, Complexity, and Controversy
14 Architecture of the Intel 80386
15 A comparison of full and partial predicated execution support for ILP processors
16 The IBM System 360 Model 91 Machine Philosophy and Instruction Handling
17 Implementing Precise Interrupts in Pipelined Processors
18 A Study of Branch Prediction Strategies
19 Two Level Adaptive Branch Prediction
20 HPS, A New Microarchitecture Introduction and Rationale
21 Instruction Issue Logic for High Performance, Interruptable Pipelined Processors
22 Machine organization of the IBM RlSC System6000 processor
23 The Mips R10000 superscalar microprocessor
24 Instruction level parallel processing history, overview, and perspective
25 A Preliminary Architecture for a Basic Data Flow Processo
26 Executing a program on the MIT tagged_token dataflow architecture
27 Architecture and Applications of the HEP Multiprocessor Computer
28 Exploiting Choice Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
29 Slave Memories and Dynamic Storage Allocation
30 Structural aspects of the System 360 Model 85, Part II The cache
31 Lockup Free Instruction FetchPrefetch Cache Organization
32 Using Cache Memory to Reduce Processor Memory Traffic
33 Improving Direct Mapped Cache Performance by the Addition of a Small
34 One level storage system
35 Performance of the VAX 11780 Translation Buffer Simulation and Measurement
36 Organization and performance of a two level virtual real cache hierarchy
37 A sequencing based taxonomy of I0 systems and review of Historical Machines
38 An Introduction to Disk Drive Modeling
39 A Case for Redundant Arrays of Inexpensive Disks
40 Ethernet distributed packet switching for local computer networks
41 A Survey of Wormhole Routing Techniques in Direct Networks
42 Reality Engine Graphics
43 Very High Speed Computing Systems
44 The Burroughs Scientific Processor (BSP)
45 Processing in Memory The Terasys Massively Parallel PIM Array
46 Reflections in a pool of processors An experience report on C mmp Hydra
47 How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
48 A New Solution to Coherence Problems in Multicache Systems
49 The Stanford DASH Multiprocessor
50 DDM - A Cache Only Memory Architecture
51 The Cosmic Cube
52 Memory Coherence in Shared Virtual Memory Systems
53 Architecture of the Pentium Microprocessor
54 Tuning the Pentium Pro MicroArchitecture
55 The Microprocessor Today
56 The Future of Microprocessors
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